1. Field of the Invention
The present invention relates to a voltage generating circuit for testing integrated circuits (ICs), and, in particular, to a circuit which tests the static character and dynamic character of ICs that have a comparatively large ratio between current in the steady state and current in the dynamic state as in CMOS large-scale integrated circuits (LSIs).
2. Description of the Related Art
FIG. 4 shows an exemplary prior voltage generating circuit which is used for testing a sample high density integrated semiconductor circuit. A load 1 in FIG. 4 represents an IC for which parameters such as the static and the dynamic character are to be tested. A bypass condenser (capacitor) C2 is connected to load 1 in parallel.
A direct current (DC) voltage, Vo, is supplied to the load 1 from an operational amplifier A. By feeding back the voltage Vo which is supplied to the load 1 as an input to the operational amplifier A1 along the line 3, the fluctuation of the voltage Vo which is supplied to load 1 is controlled.
It is preferable that a connecting point O, where the feedback circuit 3 connects to the input of the load 1 to tap the voltage Vo, is as near as possible to load 1.
A voltage supply 2 supplies voltage to a second input (different from the feedback input) of the operational amplifier A1. If the output voltage of a DC voltage supply 2 is Vi, the DC voltage Vo equals Vi in the steady state.
In order to measure the static character of the IC, a current detection resistor R1 and phase compensation condenser (capacitor) C1, which is connected to resistor R1 in parallel, are used to detect the current supplied to the load 1 from the operational amplifier A1.
By measuring the voltage which is generated at the both terminals of the current detection resistor R1 using a differential amplifier (not shown in FIG. 4) as an analog subtract circuit, and by converting the measured voltage into a digital voltage signal using an A/D converter (also not shown), the static character of the load 1 is measured. Specifically, by measuring the current to load 1 for each voltage when the voltage Vi of the DC voltage supply 2 is varied successively, the static character of power supply terminal of load 1 can be measured.
If an inner cell within the IC is defective, the current to the IC increases or decreases in a manner which is not comparable to a set of standard values defined for a good IC of the same structure. Thus, by varying the voltage supplied to the IC and measuring the resulting current to the IC (as reflected by the voltage across the resistor R1) a comparison can be made with the standard values so that the device can be judged as good or defective.
The bypass capacitor C2 is connected to the load 1 in parallel. Furthermore, the phase compensation capacitor C1 is connected in parallel to the current detection resistor R1. The purpose of the bypass capacitor C2 and phase compensation capacitor C1 will be described briefly below.
If the load 1 is a CMOS IC (a VLSI, for example), only several .mu.A (micro ampere) of current will pass into the load 1 as IL in the steady state, while the current IL could measure several A (ampere) during dynamic operation. If the current, IL, which enters load 1 fluctuates by large variations, a significant time may be required to detect the current fluctuation with operational amplifier A1, so that the detected current cannot be relied upon to provide an accurate measurement due to the delay.
Therefore, during the delay period, the bypass capacitor C2 operates to compensate for the fluctuation of the current IL which is sent to the load 1. That is, if the current entering load 1 is increased, the bypass capacitor C2 provides a temporary bypass path for the current. The time during which the capacitor C2 is charging to provide a bypass current path gives the operational amplifier time to adjust via the feedback loop 3 (i.e., the time is sufficient to compensate for the delay of the operational amplifier A1). If, on the other hand, the current sent to load 1 is decreased, the bypass capacitor C2 discharges a current IC2 to add to the current IL. The additional current IC2 maintains the charge current IL essentially constant for a time period approximately equal to the delay necessary for the operational amplifier A1 to respond to the voltage change.
The phase compensation capacitor C1 is provided to prevent the operation of operational amplifier A1 from becoming unstable. That is, the open loop gain of the operational amplifier A1 exhibits a roll-off of -6 dB/oct above a specific cut-off frequency. Therefore, if the bypass capacitor C2 is connected, an attenuation of -12 dB/oct is observed over the frequency f1=1/(2.pi.R1.multidot.C2) which is determined by the value of the bypass capacitor C2 and the value of the current detection resistor R1.
If the cutoff frequency associated with the capacitor C2 crosses the 0 dB (unity gain) region of operation of the operational amplifier A1, then this may cause the amplifier to oscillate, so that the operation of the amplifier A1 becomes unstable. To prevent instability, the attenuation characteristics of the operational amplifier circuit are compensated to restore the original -6 dB/oct roll-off before reaching the 0 dB frequency.
For this purpose, the phase compensation capacitor C1 is inserted. The cut-off frequency associated with the capacitor C1 is f2=1/(2.pi.R1.multidot.C1).
According to this circuit, the voltage Vo supplied to the load 1 can be changed by changing the voltage Vi given from DC voltage supply 2.
Since the current IL sent to load 1 and the current Io passing through the resistor R1 of the current detection circuit are the same in the steady state, Io=IL=Vm/R1 is obtained by voltage Vm output from A/D converter.
The internal resistance RX of load 1 can be calculated using the equation RX=Vo/Io=Vi.multidot.R1/Vm. Based upon the fluctuation of the internal resistance RX indicated by the fluctuation of input voltage Vo, i.e., the static character can be measured.
The following can be understood from the above explanation.
(1) If the current Io running in the steady state is very small, the resistance value of the current detection resistor R1 is large.
(2) Phase compensation capacitor C1 should be connected to the current detection resistor R1 in parallel.
(3) The bypass capacitor C2 is needed for optimum operation of the circuit.
Using this power supply circuit, a static character test of load 1 is performed and then a functional test is performed with the same measurement apparatus for the IC's which pass the static character test.
The functional test is performed by supplying input signal patterns to a plurality of signal input pins of the LSI. By measuring the output signal patterns provided on the signal output pins, and by comparing the signal patterns taken out with an expected pattern already prepared from a LSI which is known to be good, a determination can be made if the tested LSI is functioning correctly.
Therefore, it is desirable that the power supply voltage which is supplied to load 1 in the functional test is steady.
The state of voltage and current at each point in the conventional circuit of FIG. 4 will be described here with reference to FIG. 5.
FIG. 5A shows load current IL in the steady voltage operation when load 1 is inversed. The time t10 is the rise time of current sent to load 1.
Though the current IO starts to increase gradually with the increase of load current IL as shown in FIG. 5B, the increase of the current IO in response to the load current does not begin immediately because of the delay introduced by the operational amplifier A1.
In order to compensate for this delay, the bypass capacitor C2 discharges the current IC2 to load 1 (FIG. 5C). For this reason, the voltage Vo across the bypass capacitor C2 drops (as shown in FIG. 5D).
The voltage Vo is fed back to the inverting input of the amplifier A1 via the feed-back circuit 3. Because of the voltage drop across the bypass capacitor C2, i.e., the drop of voltage Vo at the point O connecting with feedback circuit 3, the charge current IO (FIG. 5B) starts to increase rapidly from the output of the operational amplifier A1 to the bypass capacitor C2.
As the current IO flows through the current detection resistor R1, so that a voltage drop of Vx=R1.multidot.IO is generated across the terminals of resistor R1. Therefore, the voltage VA at the output terminal of the operational amplifier A1 fluctuates as shown in FIG. 5E.
After a time duration t20 of charging the bypass capacitor C2, the current IO starts to decrease and after a time duration t30, the state becomes steady in inverse operation and the current IO becomes equal to the load current IL.
When load 1 returns to steady state after a fall time t11, the character of the voltage and the current at each point is the inverse of the character of the voltage and current during the rise time, as graphically depicted in FIGS. 5C and 5E.
That is, though the load current IL decreases, the current IO keeps on flowing from operational amplifier A1 in response. However, due to the feedback circuit delays, the bypass capacitor C2 is required to provide the extra current temporarily.
Though t20, t30, t21 and t31 are decided by the overall frequency characteristics of the operational amplifier A1, the resistor R1, the capacitor C1, C2, etc., which constitute the configuration of the feedback circuit, the frequency characteristics of the operational amplifier A1 dominate.
Generally, t1X&lt;&lt;t2X&lt;&lt;t3X.
When performing a functional test of load 1 using the voltage generating circuit for IC testing, the voltage Vo supplied to load 1 fluctuates by .+-.Vx voltage large within the rise time and the fall time as shown in FIG. 5D.
For example, for the case where R1=0.1.OMEGA. and Io=5A, the voltage Vo supplied to load 1 fluctuates by as much as 0.5 v. If the voltage Vo fluctuates significantly, the LSI within the load 1 could malfunction or, in the worst case, the large voltage fluctuations could damage the load 1. Furthermore, too much time may be required to judge when the voltage has become stable.